Transformation of VHDL descriptions into DEVS models for fault modeling

We propose in this article an approach for the transformation of VHDL descriptions into DEVS models for an easy and fast fault simulation. VHDL allows description of the structure of a design, that is how it is decomposed into sub-designs, and how those designs are interconnected. The specification of the function of designs are performed using familiar programming language forms. One of the main problems is that today tools are unable to quickly and easily create and simulate fault models directly from the VHDL descriptions. A way to solve this problem is to encapsulate these descriptions in easily simulating and evolutive models. We propose to use the DEVS formalism to achieve this encapsulation.