Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC

Author

Khan, Aurangzeb ; Patel, Kaushik ; Aurora, Amit ; Raza, Adnan ; Parruck, Bidyut ; Bagchi, Anandarup ; Ghosh, Abijit ; Litinsky, Boris ; Hong, Eric ; Zhao, Eric ; Ngo, Jeremy ; Ko, Kenson ; Singh, Leena ; Arnaudov, P. ; Wu, Peter ; Ramakrishnan, Rama ; Zec

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

35

Lastpage

38

Abstract

A consistent, fully hierarchical design methodology and design techniques developed to create the first single-chip full-duplex OC48 traffic manager and ATM SAR (segmentation and reassembly) IC are presented. The IC achieves a sustained throughput of 5 Gbps for 1 M simultaneous SAR flows. ∼78 M transistors are integrated in a 0.15 μm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.

Keywords

CMOS integrated circuits; asynchronous transfer mode; integrated circuit design; system-on-chip; telecommunication traffic; 0.15 micron; 5 Gbit/s; ATM SAR SoC; CMOS; IC throughput; OC48 traffic manager; SAR flows; asynchronous transfer mode; network processor; networking IC design; segmentation/reassembly IC; single-chip full-duplex traffic manager; Application specific integrated circuits; Asynchronous transfer mode; Design methodology; Fabrics; Job shop scheduling; Process control; SONET; Signal design; Switches; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249354

Filename

1249354