Analyzing the impact of supply and substrate noise on jitter in Gb/s serial links

In this paper, we quantify the impact of integrating large numbers of serializer-deserializer (SERDES) macros in an ASIC chip. The impact of core induced supply and substrate noise on peripheral high-speed SERDES macros is studied. Techniques are presented which help speed up the extraction of the detailed substrate network in a large SERDES macro, which is needed for accurate power supply noise analysis. We provide a simulation methodology for quantifying the impact of supply noise on the jitter performance of a SERDES macro placed in a large ASIC chip. We support this methodology with measurements made on a chip with a large number of SERDES macros and a core noise generator.