Proximity communication

This paper reports results from wireless chip to chip communication experiments. Sixteen bit words pass from one chip to another in parallel without detectable error at 1.35 billion data items per second for a total data rate of 21.6 gigabits per second. The experiment transmits pseudo random patterns between chips built in 350 nm CMOS technology. Chips touch face-to-face to communicate. The same pseudo random data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated. Each communication channel consumes a static power of 3.6 milliwatts, and a dynamic power of 3.9 picojoules per bit communicated. The channels lie on 50 micron centers. Since the capacitive communication works through covering oxide, ESD protection is unnecessary. Vernier position measuring circuits built into the chips indicate the relative position of transmitting and receiving arrays to assist mechanical alignment. The test chip includes a Vernier circuit that provides inter-chip position measurements with a resolution of 1.4 microns.