Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard

Author

Bertoni, Guido ; Breveglieri, Luca ; Koren, Israel ; Maistri, Paolo ; Piuri, Vincenzo

Author_Institution

Dept. of Electron. & Inf. Technol., Politecnico di Milano, Italy

fYear

2003

fDate

3-5 Nov. 2003

Firstpage

105

Lastpage

113

Abstract

Concurrent fault detection for hardware implementations of the Advanced Encryption Standard (AES) may provide protection against random faults, and against an attacker who may maliciously inject faults in order to find the encryption secret key. We have recently developed such a scheme which is based on the parity code. In this paper we prove that the parity-based code detects all odd-order faults and allows the location of most single transient and permanent faults.

Keywords

VLSI; cryptography; fault location; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; parity check codes; telecommunication security; telecommunication standards; AES; Advanced Encryption Standard; VLSI implementations; concurrent fault detection; encryption secret key; fault injection; fault location; hardware implementations; odd-order faults; parity code; permanent faults; random fault protection; single transient faults; Cryptography; Fault detection; Fault tolerant systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2042-1

Type

conf

DOI

10.1109/DFTVS.2003.1250101

Filename

1250101