Title :
Detailed comparison of dependability analyses performed at RT and gate levels
Author :
Ammari, A. ; Leveugle, R. ; Sonza-Reorda, M. ; Violante, M.
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
Methods allowing a designer to perform early dependability analyses aim either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. In the two cases, these methods can be applied at several description levels, starting from the behavioral level down to the gate level with back annotation data. This paper compares results obtained at RT and gate levels. The advantages of combining an error propagation path analysis and a classification are also discussed.
Keywords :
circuit simulation; failure analysis; integrated circuit design; integrated circuit reliability; logic design; logic simulation; transient response; RT level dependability analysis; error propagation analysis; error propagation path analysis; failure analysis; fault classification; gate level dependability analysis; transient faults; CMOS technology; Circuit faults; Electrical fault detection; Electronic mail; Error analysis; Failure analysis; Fault detection; Fault diagnosis; Performance analysis; Process design;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
Print_ISBN :
0-7695-2042-1
DOI :
10.1109/DFTVS.2003.1250129
