Detailed comparison of dependability analyses performed at RT and gate levels

Methods allowing a designer to perform early dependability analyses aim either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. In the two cases, these methods can be applied at several description levels, starting from the behavioral level down to the gate level with back annotation data. This paper compares results obtained at RT and gate levels. The advantages of combining an error propagation path analysis and a classification are also discussed.