Modeling IP responses in test case generation for systems-on-chip verification

Systems-on-chip (SoCs) are growing in complexity, and, as a consequence, getting more difficult to verify. An added challenge involves verifying system correctness in the presence of various responses produced by IP blocks in a SoC. The Transgen methodology was developed a solution for random test case generation for SoC system verification. We demonstrate how Transgen handles the issue of random response generation for SoC tests. We discuss how the lack of complete temporal information during testcase generation causes prediction errors. Finally, we explore the various heuristics used to minimize the effect of these errors on the, verification effort.