Automated bus generation for multiprocessor SoC design

The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus synthesis toot (BusSyn) uses this methodology to generate five different bus systems as examples: Bi-FIFO bus architecture (BFBA), global bus architecture version I (GBAVI), global bus architecture version III (GBA VIII), hybrid bus architecture (hybrid) and split bus architecture (SplitBA). We verify and evaluate the performance of each bus system in the context of two applications: an orthogonal frequency division multiplexing (OFDM) wireless transmitter and an MPEG2 decoder. This methodology gives the designer a great benefit in fast design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types and software programming style. In this paper, we show that BusSyn can generate buses that achieve superior performance when compared to a simple general global bus architecture (GGBA) (e.g., 16.44% performance improvement in the case of the OFDM transmitter) or when compared to the coreconnect bus architecture (CCBA) (e.g., 15.54% performance improvement in the case of the MPEG2 decoder). In addition, the bus architecture generated by BusSyn is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.