DocumentCode :
400464
Title :
A fully self-timed bit-serial pipeline architecture for embedded systems
Author :
Rettberg, Achim ; Zanella, Mauro ; Bobda, Christophe ; Lehmann, Thomas
Author_Institution :
Paderborn Univ., Germany
fYear :
2003
fDate :
2003
Firstpage :
1130
Lastpage :
1131
Abstract :
The presented architecture has the peculiar feature of being self-timed and comprising a fully interlocked pipelining structure which aims at controlling the different computational paths of a system design. One example is the automotive industry where performance, space, cost, size, and weight are of vital importance, the main features of this architecture.
Keywords :
digital signal processing chips; embedded systems; pipeline processing; computational paths; cost; embedded systems; fully interlocked pipelining structure; fully self-timed bit-serial pipeline architecture; size; space; weight; Automatic control; Centralized control; Counting circuits; Embedded system; Minimization; Pipelines; Shift registers; Signal processing algorithms; Synchronization; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253767
Filename :
1253767
Link To Document :
بازگشت