Title :
FFT Processor IP Cores synthesis on the base of configurable pipeline architecture
Author :
Melnyk, Anatoly ; Dunets, Bohdan
Author_Institution :
INTRON Ltd., Lviv, Ukraine
Abstract :
The INTRON FFT Processor IP Cores Generator, based on newest INTRON IP Core Generator creation methodology, which allows generating optimized FFT IP Cores on base of scalable source IT modules is presented.
Keywords :
digital signal processing chips; discrete Fourier transforms; field programmable gate arrays; hardware description languages; hardware-software codesign; pipeline processing; reconfigurable architectures; FFT processor IP cores synthesis; FPGA; VHDL; configurable pipeline architecture; discrete Fourier transform; high-speed cores; optimized cores; scalable source IP modules; user-defined parameters; Clocks; Discrete Fourier transforms; Fast Fourier transforms; Field programmable gate arrays; Hardware design languages; Image processing; Optimization methods; Pipelines; Signal processing; Test pattern generators;
Conference_Titel :
CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. The Experience of Designing and Application of
Print_ISBN :
966-553-278-2
DOI :
10.1109/CADSM.2003.1255034
