DocumentCode :
400715
Title :
An enhanced multilevel algorithm for circuit placement
Author :
Chan, Tony F. ; Jason Cong ; Kong, Tim ; Shinnerl, Joseph R. ; Sze, Kenton
Author_Institution :
Math. Dept., UCLA, Los Angels, CA, USA
fYear :
2003
fDate :
9-13 Nov. 2003
Firstpage :
299
Lastpage :
306
Abstract :
This paper presents several important enhancements to the recently published multilevel placement package mPL. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to GORDIAN-L-DOMINO on uniform-cell-size IBM/ISPD98 benchmarks, a speed-up of well over 8/spl times/ on large circuits (/spl ges/100,000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon on the same benchmarks, a speed-up of about 5/spl times/ is obtained at the cost of about 4% increased wirelength. On the recently published PEKO synthetic benchmarks, mPL2 generates surprisingly high-quality placements-roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon-in run time about twice as long as Capo´s and about 1/10th of Dragon´s.
Keywords :
circuit layout CAD; differential equations; interpolation; iterative methods; quadratic programming; AMG; GORDIAN-L-DOMINO; IBM/ISPD98 benchmarks; PEKO synthetic benchmark; algebraic multigrid; circuit placement; declustering; enhanced multilevel algorithm; improved interpolation; iterated V-cycles; mPL; noncontiguous subproblems; unconstrained quadratic relaxation; wirelength; Algorithm design and analysis; Circuit analysis computing; Computer science; Costs; Design automation; Interpolation; Mathematics; Packaging; Scalability; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
Type :
conf
DOI :
10.1109/ICCAD.2003.159704
Filename :
1257683
Link To Document :
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