DocumentCode :
400758
Title :
Incremental placement for timing optimization
Author :
Choi, Wonjwn ; Bazargan, K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
2003
fDate :
9-13 Nov. 2003
Firstpage :
463
Lastpage :
466
Abstract :
An incremental timing driven placement algorithm is presented. We introduce a fast path-based analytical approach for timing improvement. Our method achieves timing optimization by reducing the enclosing bounding boxes of selected nets on critical paths. Furthermore, this technique tries to minimize modifications to the initial placement while improving the delay of the circuit incrementally. Two contributions of this work are 1) efficient conversion of a path-based timing minimization problem to a geometric net-constraint problem and 2) minimal modification of a placement to improve timing. Our technique can take an initial placement from any algorithm and improve timing iteratively. The experiments show that the proposed approach is very efficient.
Keywords :
circuit layout CAD; delays; minimisation; timing; bounding boxes; circuit delay; critical paths; geometric net-constraint problem; incremental timing driven placement algorithm; path based analytical approach; path based timing minimization problem; timing optimization; Algorithm design and analysis; Circuits; Constraint optimization; Delay; Design optimization; Minimization; Routing; Runtime; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
Type :
conf
DOI :
10.1109/ICCAD.2003.159724
Filename :
1257851
Link To Document :
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