DocumentCode :
400772
Title :
A probabilistic approach to buffer insertion
Author :
Khandelwal, Vishal ; Davoodi, Azadeh ; Nanavati, Akash ; Srivastava, Ankur
Author_Institution :
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
fYear :
2003
fDate :
9-13 Nov. 2003
Firstpage :
560
Lastpage :
567
Abstract :
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flow. This can be attributed mainly to unawareness of low level layout information and variability in fabrication process. Hence a traditional deterministic design automation approach where each cost function is represented as a fixed value becomes obsolete. A new approach is gaining attention in which the cost functions are represented as probability distributions and the optimization criteria is probabilistic too. This design optimization philosophy is demonstrated through the classic buffer insertion problem. Formally, we capture wirelengths as probability distributions (as compared to the traditional approach which considers wirelength as fixed values) and present several strategies for optimizing the probabilistic criteria. During the course of this work many problems are proved to be NP-Complete. Comparisons are made with the Van-Ginneken "optimal under fixed wire-length" algorithm. Results show that the Van-Ginneken approach generated delay distributions at the root of the fanout wiring tree which had large probability (0.91 in the worst case and 0.55 on average) of violating the delay constraint. Our algorithms could achieve 100% probability of satisfying the delay constraint with similar buffer penalty. Although this work considers wirelength prediction inaccuracies, our probabilistic strategy could be extended trivially to consider fabrication variability in wire parasitics.
Keywords :
buffer circuits; circuit optimisation; electronic design automation; probability; NP-complete problems; Van-Ginneken approach; buffer insertion; cost function; delay constraint; delay distributions; design automation; design optimization; probabilistic approach; probability distributions; wirelength prediction; wiring tree; Accuracy; Computer science; Cost function; Delay estimation; Design automation; Design optimization; Educational institutions; Fabrication; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
Type :
conf
DOI :
10.1109/ICCAD.2003.159738
Filename :
1257866
Link To Document :
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