Simultaneous analytic area and power optimization for repeater insertion

Author

Garcea, Giuseppe S. ; Van Der Meijs, Nick P. ; Otten, Ralph H J M

Author_Institution

Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

2003

fDate

9-13 Nov. 2003

Firstpage

568

Lastpage

573

Abstract

We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance /spl tau//sub crit//K where /spl tau//sub crit/, is the minimum possible delay along a global interconnect, with repeaters inserted, and 0 \n\n\t\t

Keywords

Pareto optimisation; interconnections; minimisation; power consumption; repeaters; wires (electric); analytic area optimization; buffer insertion; critical segments screening; global interconnects; interconnect characterization data; pareto-optimal repeater insertion theory; position constraints; power dissipation minimisation; power optimization; silicon device area minimisation; wire geometry; Delay; Geometry; Pareto analysis; Performance analysis; Power dissipation; Repeaters; Routing; Silicon devices; Switches; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Aided Design, 2003. ICCAD-2003. International Conference on

Conference_Location

San Jose, CA, USA

Print_ISBN

1-58113-762-1

Type

conf

DOI

10.1109/ICCAD.2003.159739

Filename

1257867

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=400773