Branch merge reduction of RLCM networks

In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted at parasitic extractors for verification of VLSI designs, the proposed algorithm uses a branch merge, node elimination methodology, with the choice of nodes for elimination being guided by time-constant criteria. Reliable, accurate, easy to code, the algorithm works well for coupled buses and clocks, strongly inductive networks, and low-loss transmission lines, as well as for lossy RLC networks.