ATPG for noise-induced switch failures in domino logic

Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with technology scaling, domino circuits are increasingly susceptible to switch failures due to various noise sources that include crosstalk, charge sharing and leakage. To test for such failures in a manufactured chip, we describe a test pattern generation methodology that generates specific test patterns to target such failures. These test patterns activate noise from multiple sources such that their combined effect causes a switch failure at a domino gate output. In addition, the test patterns propagate the resulting error to an observable output within the duration of the circuit´s clock cycle. The methodology has been implemented and validated using a domino multiplier circuit.