DocumentCode
400799
Title
Multi-domain clock skew scheduling
Author
Ravindran, Kaushik ; Kuehlmann, Andreas ; Sentovich, Ellen
Author_Institution
California Univ., Berkeley, CA, USA
fYear
2003
fDate
9-13 Nov. 2003
Firstpage
801
Lastpage
808
Abstract
The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner. This results in a significant limitation of the optimization potential. As an alternative, the application of multiple clocking domains with dedicated phase shifts that are implemented by reliable, possibly expensive design structures can overcome these limitations and substantially increase the implementable optimization potential of clock adjustments. In this paper we present an algorithm for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within-domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Our experiments demonstrate that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.
Keywords
clocks; delays; optimisation; phase shifters; scheduling; clock delays; domain latency; multidomain clock skew scheduling; multiple clocking domains; optimal phase shifts; optimization potential; unconstrained clock schedule; zero skew clock delivery; Circuits; Clocks; Delay; Frequency; Permission; Processor scheduling; Registers; Scheduling algorithm; Timing; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
1-58113-762-1
Type
conf
DOI
10.1109/ICCAD.2003.159768
Filename
1257900
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