Towards the complete elimination of gate/switch level simulations

This paper presents the reasoning behind eliminating full-chip gate/switch-level simulations for microprocessors/digital system designs and utilizing RTL models for the purpose, provided formal boolean equivalence between RTL and gate/switch-level models have been established using symbolic simulation for all blocks that comprise the chip. No logic bug should go undetected if only RTL models are used for full chip simulations provided existing design methodologies are enhanced to incorporate a constraints checking flow coupled with a rigorous circuit metastability/contention prevention flow.