• DocumentCode
    402095
  • Title

    Program slicing for ATPG-based property checking

  • Author

    Vedula, Vivekananda M. ; Townsend, Whitney J. ; Abraham, Jacob A.

  • Author_Institution
    Texas Dev. Center, Intel Corp., Austin, TX, USA
  • fYear
    2004
  • fDate
    2004
  • Firstpage
    591
  • Lastpage
    596
  • Abstract
    This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (SAT) techniques, are beginning to be widely used for checking properties of designs. Recent approaches using sequential ATPG techniques, which harness the structural information of the design, have been shown to perform better than SAT-based BMC. However, these techniques require an effective methodology to deal with the size of commercial designs. A program slicing methodology that has been shown to accelerate sequential ATPG is adapted and integrated into an ATPG-based BMC framework. Furthermore, a generalization of the ATPG-based approach, which checks for unbounded liveness, is also presented.
  • Keywords
    automatic test pattern generation; computability; program slicing; program verification; sequential circuits; ATPG based property checking; abstracting designs; automatic test pattern generation; bounded model checking; program slicing; satisfiability techniques; sequential ATPG techniques; Acceleration; Automatic test pattern generation; Boolean functions; Contracts; Data structures; Design engineering; Integrated circuit synthesis; Jacobian matrices; Scalability; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2004. Proceedings. 17th International Conference on
  • Print_ISBN
    0-7695-2072-3
  • Type

    conf

  • DOI
    10.1109/ICVD.2004.1260983
  • Filename
    1260983