Preventing crosstalk delay using Fibonacci representation

As the CMOS technology scaled down to deep sub-micron level, the crosstalk effects due to the coupling capacitance between interconnection lines has become one of the main performance limiting factors. Several methods such as those based on routing strategies, skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, precharging the bus, and bus encoding technique, have been proposed to eliminate/reduce the crosstalk delay. In this work, we propose a bus encoding technique using a variant of binary Fibonacci representation to prevent crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. We show that m-bit crosstalk delay free binary Fibonacci codewords are used to encode └log₂(F_m+2)┘-bit bus, where F_m+2 is the (m+2)^th Fibonacci number. So, a 32-bit bus can be encoded using 46-bit crosstalk delay free binary Fibonacci codewords.