Title :
Large-scale network simulations with GTNetS
Author :
Riley, George F.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
When designing a network simulation environment intended specifically for modeling large-scale topologies, a number of issues must be addressed by the simulator designer. Memory requirements for network simulation engines can grow quadratically with the size of the simulated topology and can easily exceed available memory on modern workstations. The number of outstanding simulation events grows linearly with the number of packets in flight being modeled, and can lead to performance bottlenecks when managing a sorted event list of millions of events. Tracking the results of the simulation using a packet-level log file can result in excessive usage of disk space. We discuss the design of the Georgia Tech Network Simulator (GTNetS) with emphasis on how GTNetS addresses these issues. We give results from performance experiments showing the reduction in memory and event list size as a result of our design decisions.
Keywords :
computational complexity; computer networks; digital simulation; software packages; workstation clusters; GTNetS; Georgia Tech Network Simulator; design decisions; disk space usage; event list size; large-scale network simulations; large-scale topologies; memory reduction; memory requirements; network simulation engines; network simulation environment design; packet-level log file; performance bottlenecks; performance experiments; simulation events; workstations; Analytical models; Computational modeling; Computer networks; Computer simulation; Discrete event simulation; Educational institutions; Large-scale systems; Network topology; Protocols; Scalability;
Conference_Titel :
Simulation Conference, 2003. Proceedings of the 2003 Winter
Print_ISBN :
0-7803-8131-9
DOI :
10.1109/WSC.2003.1261483