Title :
From timed automata to DEVS models
Author :
Giambiasi, Norbert ; Paillet, Jean-Luc ; Cháne, Frédéric
Author_Institution :
LSIS, Univ. Aix-Marsielle III, Marsielle, France
Abstract :
In this paper, we present the formal transformation of Timed Input/Output Automata into simulation models, expressed in the DEVS formalism. This transformation takes place in an approach of a validation of high-level specifications by simulation. The validation is based on the simulation of a coupled model built with the system to be controlled and the control specifications. An example of this approach is given in the paper.
Keywords :
digital simulation; finite automata; formal specification; formal verification; DEVS models; Timed Input/Output Automata; control specifications; coupled model; formal transformation; high-level specification validation; simulation models; timed automata; Automata; Automatic control; Clocks; Control system synthesis; Control systems; Formal specifications; Timing;
Conference_Titel :
Simulation Conference, 2003. Proceedings of the 2003 Winter
Print_ISBN :
0-7803-8131-9
DOI :
10.1109/WSC.2003.1261512
