Bias circuit topologies for minimization of RF amplifier memory effects

Memory effects in amplifiers can be described as the dependence of the output signal not only to the instantaneous input, but also to previous inputs. In a system where these effects exist, the linearity of the amplifier is degraded by the DC supply impedance, which is affected by changes in the instantaneous bandwidth of the input signal. The resulting nonlinearity is difficult to remove completely, even by the most sophisticated predistortion techniques. This paper describes a circuit technique that is readily applicable to RF amplifiers designed for wideband applications used with or without a lineariser. The memory effect reduction is achieved by placing transmission zeros in the bias network transfer function. Transmission zeros at the output of device are formed by utilizing the series resonance properties of decoupling capacitors. The frequency response is synthesized to lower and even out the impedance of the bias network over the resulting distortion bandwidth.