Title :
Designing interconnection networks for multi-level packaging
Author :
Raghunath, M.T. ; Ranade, Abhiram
Author_Institution :
Comput. Sci. Div., California Univ., Berkeley, CA, USA
Abstract :
A central problem in building large scale parallel machines is the design of the interconnection network. Interconnection network design is largely constrained by packaging technology. The authors start with a generic set of packaging restrictions and evaluate different network organizations under a random traffic model. They identify families of networks (product of complete graphs, high degree deBruijn graphs) that they believe will be useful for multilevel packaging. The results indicate that customizing the network topology to the packaging constraints is useful. Some of the general principles that arise out of this study are: (1) making the networks denser at the lower levels of the packaging hierarchy has a significant positive impact on global communication performance, (2) it is better to organize a fixed amount of communication bandwidth as a smaller number of high bandwidth channels, and (3) providing the processors with the ability to tolerate latencies (by using multithreading) is very useful in improving performance.
Keywords :
multiprocessor interconnection networks; packaging; communication bandwidth; complete graphs; generic set; global communication performance; high bandwidth channels; high degree deBruijn graphs; interconnection networks design; large scale parallel machines; latencies; multilevel packaging; multithreading; network organizations; network topology; packaging constraints; packaging hierarchy; packaging restrictions; packaging technology; random traffic model; Bandwidth; Buildings; Global communication; Large-scale systems; Multiprocessor interconnection networks; Network topology; Packaging machines; Parallel machines; Telecommunication traffic; Traffic control;
Conference_Titel :
Supercomputing '93. Proceedings
Print_ISBN :
0-8186-4340-4
DOI :
10.1109/SUPERC.1993.1263535