DocumentCode :
402674
Title :
A scheduler-sensitive global register allocator
Author :
Norris, Cindy ; Pollock, Lori L.
Author_Institution :
Dept. of Comput. & Inf. Sci., Delaware Univ., Newark, DE, USA
fYear :
1993
fDate :
15-19 Nov. 1993
Firstpage :
804
Lastpage :
813
Abstract :
Compile-time reordering of machine-level instructions has been very successful at achieving large increases in performance of programs on machines offering fine-grained parallelism. However, because of the interdependences between instruction scheduling and register allocation, it is not clear which of these two phases of the compiler should run first to generate the most efficient final code. The authors describe their investigation into slight modifications to key phases of a successful global register allocator to create a scheduler-sensitive register allocator, which is then followed by an off-the-shelf instruction scheduler. These experimental studies reveal that this approach achieves speedups comparable and increasingly better than previous cooperative approaches with an increasing number of available registers without the complexities of the previous approaches.
Keywords :
parallel processing; processor scheduling; program compilers; storage allocation; compile-time reordering; cooperative approaches; fine-grained parallelism; instruction scheduling; machine-level instructions; off-the-shelf instruction scheduler; register allocation; scheduler-sensitive global register allocator; speedups; Concurrent computing; Delay; Niobium compounds; Parallel processing; Processor scheduling; Program processors; Registers; Runtime; Supercomputers; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Supercomputing '93. Proceedings
ISSN :
1063-9535
Print_ISBN :
0-8186-4340-4
Type :
conf
DOI :
10.1109/SUPERC.1993.1263538
Filename :
1263538
Link To Document :
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