Title :
Opportunities and challenges in building silicon products in 65nm and beyond
Author :
Spirakis, Gregory S.
Author_Institution :
Intel, Santa Clara, CA, USA
Abstract :
The demand for cheaper, faster and more integrated semiconductor products is expected to drive the scaling of silicon technology, enabling continuance of Moore´s law at least for another decade. However, technology scaling presents several manufacturing and design technology challenges that must be overcome to build semiconductor products in a cost effective manner. While some of the existing challenges that we face today such as power, process variations are expected to become worse at smaller geometries requiring innovations, new problems may arise in integrating heterogeneous technologies such as RF, MEMS on the same die/package. A myriad of design technology challenges starting from functional validation to timing validation and design for test to manufacturability must be addressed to successfully build products. The paper will highlight challenges and identify some of the opportunities in driving design technologies forward.
Keywords :
design for manufacture; design for testability; elemental semiconductors; integrated circuit design; integrated circuit modelling; silicon; 65 nm; MEMS; Moore law; RF; Si; design for test; design technology; functional validation; heterogeneous technologies; integrated semiconductor products; silicon products; silicon technology; technology scaling; timing validation; Buildings; Costs; Geometry; Micromechanical devices; Moore´s Law; Radio frequency; Semiconductor device manufacture; Semiconductor device packaging; Silicon; Technological innovation;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1268818