Digital background gain error correction in pipeline ADCs

Author

Ginés, Antonio J. ; Peralías, Eduardo J. ; Rueda, Adoración

Author_Institution

Instituto de Microelectonica de Sevilla, Centro Nacional de Microelectron., Sevilla, Spain

Volume

1

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

82

Abstract

This paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Keywords

analogue-digital conversion; calibration; error correction; gain measurement; MDAC; analogue-to-digital converter; background calibration; digital background; digital noise signal; digital technique; dynamic rate; gain error correction; input-output characteristics; on-line calibration; pipeline ADC; Analog-digital conversion; Bandwidth; Calibration; Error correction; Linearity; Performance evaluation; Performance gain; Pipelines; Power measurement; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1268831

Filename

1268831