DocumentCode :
403510
Title :
Time-energy design space exploration for multi-layer memory architectures
Author :
Szymanek, Radoslaw ; Catthoor, Francky ; Kuchcinski, Krzysztof
Author_Institution :
Dept. of Comput. Sci., Lund Univ., Sweden
Volume :
1
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
318
Abstract :
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the quality of the results and its runtime depending on the used metrics and the number of levels in the hierarchical composition of the tasks´ Pareto points. We have evaluated our algorithm on a medical image processing application and randomly generated task graphs. We have shown that our algorithm can explore huge design space and obtain (near) optimal results in terms of Pareto diagram quality.
Keywords :
Pareto optimisation; integrated circuit design; memory architecture; Pareto diagrams; Pareto trade-off points; algorithm; energy consumption; execution time; exploration algorithm; hierarchical composition; medical image processing application; multi-objective execution options; multilayer memory architectures; parameterized memory architecture; scheduling; space exploration; task graph; time-energy design; Algorithm design and analysis; Application software; Bandwidth; Computer architecture; Computer science; Energy consumption; Memory architecture; Memory management; Scheduling; Space exploration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268867
Filename :
1268867
Link To Document :
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