DocumentCode :
403513
Title :
A system level exploration platform and methodology for network applications based on configurable processors
Author :
Quinn, D. ; Lavigueur, B. ; Bois, G. ; Aboulhamid, M.
Author_Institution :
Ecole Polytechnique de Montreal, Que., Canada
Volume :
1
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
364
Abstract :
A recent practice in the development of programmable SoC is the integration of configurable processors, since they offer an interesting compromise between purely software and hardware solutions. This paper proposes an adjustment to the current codesign approach to integrate this opportunity at the partitioning level. Since configurable processors seem to be an interesting option for NPU designs, we integrated into a system level exploration platform the support of an Xtensa processor for more investigation. As case studies, this paper illustrates the methodology for two realistic network-processing applications, for which interesting performances are obtained.
Keywords :
circuit CAD; integrated circuit design; microprocessor chips; reconfigurable architectures; system-on-chip; NPU designs; Xtensa processor; codesign approach; configurable processors; hardware solutions; network applications; programmable SoC; realistic network-processing applications; software solutions; system level exploration platform; Application software; Application specific processors; Bandwidth; Computer architecture; Design automation; Engines; Hardware; Network-on-a-chip; Software performance; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268874
Filename :
1268874
Link To Document :
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