Exploring logic block granularity for regular fabrics

Driven by the economics of design and manufacturing nanoscale integrated circuits, an emphasis is being placed on developing new, regular logic fabrics that leverage the regularity and programmability of FPGAs, yet deliver a level of performance and density close to ASICs. One example of such a fabric is a Via-Patterned Gate Array (VPGA) according to Pillegi et al. (2002), which employs ASIC style global routing on top of an array of patternable logic blocks (PLBs). Previous works (Koorapaty et al., 2003; Koorapaty, 2003; Pileggi et al., 2003) showed that by employing even limited heterogeneity for the VPGA logic blocks, namely combining a 3-LUT with two 3-input Nand gates, one can achieve performance comparable to that provided by standard cells. Since the area cost for such heterogeneity id far less for FPGAs, we can explore new configurations of via-configurable logic blocks that offer greater heterogeneity and granularity to achieve even higher performance. In this paper, we present a new, more granular, via-patterned heterogeneous logic block architecture and compare it to a less granular LUT-based heterogeneous PLB. Our results show higher performance and more effective packing of the logic functions due to increased granularity.