High-level system modeling and architecture exploration with SystemC on a network SoC: S3C2510 case study

This paper presents a high-level design methodology applied on a network SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the project with working Verilog RTL models in hands, which we later compared our SystemC models to. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL´s. The main topic of the paper will be on architecture exploration in search of performance degradation in source.