DocumentCode :
403539
Title :
On concurrent error detection with bounded latency in FSMs
Author :
Almukhaizim, Sobeeh ; Drineas, Petros ; Makris, Yiorgos
Author_Institution :
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Volume :
1
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
596
Abstract :
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, albeit at the cost of introducing a small latency in the detection of errors. In order to ensure no loss of error detection capabilities as compared to CED without latency, an upper bound is imposed on the introduced latency. We examine the necessary conditions for performing CED with bounded latency, based on which we extend a parity-based method to permit bounded latency. We formulate the problem of minimizing the number of required parity bits as an integer program and we propose an algorithm based on linear program relaxation and randomized rounding to solve it. Experimental results indicate that allowing a small bounded latency reduces the hardware cost of the CED circuitry.
Keywords :
error detection; finite state machines; logic circuits; logic design; logic testing; CED circuitry; FSM; bounded latency; combinational circuits; concurrent error detection; finite state machines; integer program; linear program relaxation; parity bit minimization; parity-based method; randomized rounding; sequential circuits; upper bound; Circuit faults; Computer errors; Convolutional codes; Costs; Delay; Electrical fault detection; Fault detection; Hardware; Sequential circuits; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268910
Filename :
1268910
Link To Document :
بازگشت