DocumentCode :
403545
Title :
Interactive cosimulation with partial evaluation
Author :
Schaumont, Patrick ; Verbauwhede, Ingrid
Author_Institution :
Dept. of Electr. Eng., Califonia Univ., Los Angeles, CA, USA
Volume :
1
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
642
Abstract :
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimization is partial evaluation. Our contribution is that we apply the optimization transparently to the user, and at multiple abstraction levels in the simulation. We use the technique to create an interactive codesign environment, and evaluate it on several designs including an AES encryption coprocessor and a Viterbi decoder, and for several instruction-set simulators. Compared to SystemC-based cosimulation, we achieve comparable cosimulation performance at only a fraction of the model-build time.
Keywords :
circuit optimisation; circuit simulation; hardware-software codesign; integrated circuit design; AES encryption coprocessor; SystemC-based cosimulation; Viterbi decoder; abstraction levels; hardware-software cosimulation; instruction-set simulators; interactive codesign environment; interactive cosimulation; partial evaluation; simulator compile-time; Automatic testing; Computer languages; Coprocessors; Cryptography; Decoding; Design automation; Embedded software; Hardware; Software testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268917
Filename :
1268917
Link To Document :
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