Communication analysis for system-on-chip design

Author

Siebenborn, A. ; Bringmann, O. ; Rosenstiel, W.

Author_Institution

FZI Forschungszentrum Informatik, Karlsruhe, Germany

Volume

1

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

648

Abstract

In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using the results of our method for communication analysis, we present a new method to detect communications that might produce conflicts on shared communication resources. This information can be used for the assignment of communication resources.

Keywords

communication complexity; hardware-software codesign; integrated circuit design; synchronisation; system-on-chip; SoC design; global timing behavior; parallel communicating processes; program flow; shared communication resources; synchronization points; system-on-chip design; Automata; Communication channels; Delay; Hardware; Instruction sets; Network-on-a-chip; Petri nets; Process design; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1268918

Filename

1268918