Title :
Automatic scan insertion and pattern generation for asynchronous circuits
Author :
Efthymiou, Aristides ; Sotiriou, Christos ; Edwards, Douglas
Author_Institution :
Dept. of Comput. Sci., Manchester Univ., UK
Abstract :
This paper presents 3ΦLSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3ΦLSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3ΦLSSD ATPG tool achieved over 99% test coverage.
Keywords :
asynchronous circuits; automatic test pattern generation; circuit feedback; clocks; logic testing; ATPG method; LSSD clocking scheme; SOC interconnection fabric; area overhead testing; asynchronous circuits; automatic pattern generation; automatic scan insertion; global circuit feedback paths; scan latches; state-storing gates; Asynchronous circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Fabrics; Feedback circuits; Integrated circuit interconnections; Latches; State feedback;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1268924