Test compression and hardware decompression for scan-based SoCs

Author

Wolff, Francis G. ; Papachristou, Chris ; McIntyre, David R.

Author_Institution

Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA

Volume

1

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

716

Abstract

We present a new decompression architecture suitable for embedded cores in SoCs which focuses on improving the download time by avoiding higher internal-to-ATE clock ratios and by exploiting hardware parallelism. The bounded Huffman compression facilitates decompression hardware tradeoffs. Our technique is scalable in that the downloadable RAM-based decode table and accommodates for different SoC cores with different characteristics such as the number of scan chains and test set data distributions.

Keywords

Huffman codes; data compression; integrated circuit testing; logic testing; system-on-chip; RAM-based decode table; bounded Huffman compression; decompression architecture; decompression hardware tradeoffs; download time reduction; embedded cores; hardware decompression; hardware parallelism; internal-to-ATE clock ratios; scan chains; scan-based SoC; test compression; test set data distributions; Automatic test pattern generation; Clocks; Computer science; Decoding; Feeds; Hardware; Parallel processing; Pins; Tellurium; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1268945

Filename

1268945