DocumentCode :
403609
Title :
Timing analysis for preemptive multi-tasking real-time systems with caches
Author :
Tan, Yudong ; Mooney, Vincent J., III
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
2
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
1034
Abstract :
In this paper, we propose an approach to estimate the worst case response time (WCRT) of tasks in a preemptive multi-tasking single-processor real-time system with a set associative cache. The approach focuses on analyzing the cache reload overhead caused by preemptions. We combine inter-task cache eviction behavior analysis and path analysis of the preempted task to reduce, in our analysis, the estimate of the number of cache lines that can possibly be evicted by the preempting task (thus requiring a reload by the preempted task). A mobile robot application which contains three tasks is used to test our approach. The experimental results show that our approach can tighten the WCRT estimate by up to 73% over prior state-of-the-art.
Keywords :
cache storage; multiprogramming; real-time systems; timing; intertask cache eviction; mobile robot; multitasking real time systems; path analysis; set associative cache; timing analysis; worst case response time; Delay; Embedded computing; Embedded system; Hardware; Mobile robots; Pipeline processing; Real time systems; State estimation; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1269029
Filename :
1269029
Link To Document :
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