DocumentCode :
403618
Title :
Boosting: min-cut placement with improved signal delay
Author :
Kahng, Andrew B. ; Markov, Igor L. ; Reda, Sherief
Author_Institution :
CSE & ECE Dept., California Univ., La Jolla, CA, USA
Volume :
2
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
1098
Abstract :
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to net spans, so as to reduce the quadratic wirelength. Our method is generic and does not involve any timing analysis during or prior to placement. In essence, we skew the netlength distribution produced by a min-cut placer so as to decrease the number of long nets, with minimal impact on the overall wirelength. Empirically this approach does not significantly affect runtime, but reduces the worst negative slack and total negative slack of industrial benchmarks by up to 70% compared to Capo and a leading industrial placer.
Keywords :
circuit layout; circuit optimisation; delays; timing; boosting factors; circuit layout; circuit optimisation; industrial benchmarks; min cut placement; netlength distribution; quadratic wirelength; signal delay; timing analysis; Boosting; Delay lines; Permission; Routing; Runtime; Scalability; Time measurement; Timing; Upper bound; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1269039
Filename :
1269039
Link To Document :
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