DocumentCode :
403643
Title :
Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets
Author :
Wang, Seongmoon ; Liu, Xiao ; Chakradhar, Srimat T.
Author_Institution :
NEC Labs., Princeton, NJ, USA
Volume :
2
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
1296
Abstract :
A novel scan-based delay test approach, referred as the hybrid delay scan, is proposed in this paper. The proposed scan-based delay testing method combines advantages of the skewed-load and broad-side approaches. Unlike the skewed-load approach whose design requirement is often too costly to meet due to the fast switching scan enable signal, the hybrid delay scan does not require a strong buffer or buffer tree to drive the fast switching scan enable signal. Hardware overhead added to standard scan designs to implement the hybrid approach is negligible. Since the fast scan enable signal is internally generated, no external pin is required. Transition delay fault coverage achieved by the hybrid approach is equal to or higher than that achieved by the broad-side load for all ISCAS 89 benchmark circuits. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach.
Keywords :
delays; logic circuits; logic testing; test equipment; timing; ISCAS 89 benchmark circuits; compact test sets; hybrid delay scan; scan based delay testing method; scan enable signal; standard scan designs; transition delay fault coverage; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Flip-flops; Hardware; National electric code; Sequential analysis; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1269074
Filename :
1269074
Link To Document :
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