A new self-checking sum-bit duplicated carry-select adder

Author

Sogomonyan, E.S. ; Marienfeld, D. ; Ocheretnij, V. ; Gössel, M.

Author_Institution

Dept. of Comput. Sci., Univ. of Potsdam, Germany

Volume

2

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

1360

Abstract

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. The area is 170% of a 64 bit carry-select adder (without error detection and not code-disjoint).

Keywords

CAD; adders; carry logic; logic gates; parity check codes; 64 bit; 64 bit carry select adder; CAD tool; EUROCHIP project; NAND gate delay; XOR; computer aided design; error detection; exclusive OR; parity; ripple adders; self checking carry select adder; self checking sum bit; Computer science; Delay; Fault tolerance; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269087

Filename

1269087