Title :
Accurate estimation of parasitic capacitances in analog circuits
Author :
Agarwal, Anuradha ; Sampath, Hemanth ; Yelamanchili, Veena ; Vemuri, Ranga
Author_Institution :
Dept. of ECECS, Cincinnati Univ., OH, USA
Abstract :
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.
Keywords :
CMOS integrated circuits; analogue circuits; capacitance; integrated circuit layout; table lookup; analog CMOS circuits; layout aware synthesis flow; parasitic capacitance estimation; parasitic capacitances modeling; parasitic models; table lookup; Analog circuits; Analog integrated circuits; CMOS analog integrated circuits; Circuit synthesis; Integrated circuit interconnections; Integrated circuit modeling; LAN interconnection; Parasitic capacitance; Semiconductor device modeling; Signal synthesis;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1269090
