Test infrastructure design for the Nexperia™ home platform PNX8550 system chip

Author

Goel, Sandeep Kumar ; Chiu, Kuoshu ; Marinissen, Erik Jan ; Nguyen, Toan ; Oostdijk, Steven

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

3

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

108

Abstract

Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia™ home platform. The on-chip infrastructure that enables modular testing consists of wrappers and test access mechanisms (TAMs). Optimizing that infrastructure minimizes the test application time and helps to fit the test data into the ATE vector memory. This paper presents the test architecture design for the chiplet-based PNX8550, the most complex Nexperia™ SOC designed to date. Significant savings in test time and TAM wires could be obtained with the help of TR-ARCHITECT, an in-house tool for automated design of SOC test architectures.

Keywords

automatic test equipment; integrated circuit design; integrated circuit testing; system-on-chip; ATE vector memory; Nexperia home platform; PNX8550 system chip; SOC test architecture design; automated design; automatic test equipment; chiplet based PNX8550; modular testing; system on chip; test access mechanism wires; test data; test infrastructure design; Automatic testing; Consumer electronics; Electronic equipment testing; Laboratories; Logic testing; Manufacturing; Semiconductor device manufacture; Semiconductor device testing; System testing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269215

Filename

1269215