Customisable EPIC processor: architecture and tools

Author

Chu, W.W.S. ; Dimond, R.G. ; Perrott, S. ; Seng, S.P. ; Luk, W.

Author_Institution

Dept. of Comput., Imperial Coll., London, UK

Volume

3

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

236

Abstract

This paper describes a customisable architecture and the associated tools for a prototype EPIC (explicitly parallel instruction computing) processor. Possible customisations include varying the number of registers and functional units, which are specified at compile-time. This facilitates the exploration of performance/area trade-off for different EPIC implementations. We describe the tools for this EPIC processor, which include a compiler and an assembler based on the trimaran framework. Various pipelined EPIC designs have been implemented using field programmable gate arrays (FPGAs); the one with 4 ALUs at 41.8 MHz can run a DCT application 5 times faster than the strongARM SA-110 processor at 100 MHz.

Keywords

field programmable gate arrays; optimising compilers; parallel processing; pipeline processing; program assemblers; 41.8 MHz; ARM SA-110 processor; FPGA; Trimaran framework; assembler; compiler; customisable architecture; explicitly parallel instruction computing processor; field programmable gate arrays; Assembly; Computer aided instruction; Computer architecture; Concurrent computing; Field programmable gate arrays; Hardware; Performance analysis; Process design; Registers; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269236

Filename

1269236