Improvement of circuit-speed of HEMTs IC by reducing the parasitic capacitance

Author

Makiyama, K. ; Takahashi, T. ; Suzuki, T. ; Sawada, K. ; Ohki, T. ; Nishi, M. ; Hara, N. ; Takikawa, M.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

We developed a novel process technology to removes the dielectric substance around gate electrodes to decrease parasitic capacitance. The process enabled us to increase the operating speed of the integrated circuit without causing any process damage. As a result, we achieved 90 GHz operation of a static T-FF circuit using InP-HEMT technology. This is the fastest T-FF, consisting of a FET, reported to date. We also showed the excellent potential of this technology for fabricating ultra-high speed ICs.

Keywords

HEMT integrated circuits; III-V semiconductors; field effect MIMIC; indium compounds; very high speed integrated circuits; 90 GHz; HEMT IC circuit-speed improvement; InP; InP-HEMT technology; gate electrode dielectric removal; operating speed increase; parasitic capacitance reduction; static T FF circuit; ultra-high speed IC; Delay; Digital circuits; Electrodes; Equations; Filling; HEMTs; Integrated circuit interconnections; Integrated circuit technology; MODFETs; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269384

Filename

1269384