• DocumentCode
    403788
  • Title

    Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories

  • Author

    Wright, Derek ; Sachdev, Manoj

  • Author_Institution
    University of Waterloo
  • Volume
    1
  • fYear
    2003
  • fDate
    Sept. 30-Oct. 2, 2003
  • Firstpage
    39
  • Lastpage
    47
  • Keywords
    Algorithm design and analysis; Associative memory; CADCAM; Cams; Computer aided manufacturing; Computer networks; Mathematical model; Random access memory; Read-write memory; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2003. Proceedings. ITC 2003. International
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-8106-8
  • Type

    conf

  • DOI
    10.1109/TEST.2003.1270823
  • Filename
    1270823
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=403788