403788

Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories

Wright, Derek ; Sachdev, Manoj

University of Waterloo

1

2003

Sept. 30-Oct. 2, 2003

39

47

Algorithm design and analysis; Associative memory; CADCAM; Cams; Computer aided manufacturing; Computer networks; Mathematical model; Random access memory; Read-write memory; Testing;

English

ieee

Test Conference, 2003. Proceedings. ITC 2003. International

1089-3539

0-7803-8106-8

conf

10.1109/TEST.2003.1270823

1270823