Title :
Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
Author :
Velev, Miroslav N.
Author_Institution :
School of Electrical and Computer Engineering, Georgia Institute of Technology
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Computer bugs; Design engineering; Engines; Formal verification; Hardware design languages; Logic design; Microprocessors; Pipelines; Predictive models; Testing;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1270834
