Title :
Area and time co-optimization for system-on-a-chip based on consecutive testability
Author :
Yoneda, Tomokazu ; Uchiyama, Tetsuo ; Fujiwara, Hideo
Author_Institution :
Graduate School of Information Science, Nara Institute of Science and Technology
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Circuit faults; Circuit testing; Clocks; Costs; Integrated circuit interconnections; Integrated circuit testing; System testing; System-on-a-chip; Time to market; Timing;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1270866
