Title :
Efficient scan chain design for power minimization during scan testing under routing constraint
Author :
Borthomme, Y. ; Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S.
Author_Institution :
Snopsys Inc.
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Circuit testing; Degradation; Design for testability; Energy consumption; Joining processes; Logic testing; Minimization; Routing; System testing; Uniform resource locators;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1270874
