Title :
Modeling scan chain modifications for scan-in test power minimization
Author :
Sinanoglu, Ozgur ; Orailoglu, Alex
Author_Institution :
University of California
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Algorithm design and analysis; Circuit testing; Computer science; Degradation; Logic gates; Mathematical analysis; Mathematical model; Power engineering and energy; Reliability engineering; Time to market;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1270887
