DocumentCode
403888
Title
Register transfer level approach to hybrid time and hardware redundancy based fault secure datapath synthesis
Author
Wu, Kaijie ; Karri, Ramesh
Author_Institution
Polytechnic University
Volume
1
fYear
2003
fDate
Sept. 30-Oct. 2, 2003
Firstpage
902
Lastpage
911
Keywords
Circuit faults; Combinational circuits; Error analysis; Frequency; Hardware; Logic devices; Redundancy; Sequential circuits; Single event upset; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2003. Proceedings. ITC 2003. International
ISSN
1089-3539
Print_ISBN
0-7803-8106-8
Type
conf
DOI
10.1109/TEST.2003.1271076
Filename
1271076
Link To Document